W88113C Datasheet, PDF (92/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
5.4.5 EDC Checking
The EDC checking logic carry 32-bit CRC checking on error corrected data according to its mode.
The checking result can be monitored through flag CRCOK (0Ch.r7). If the result is error, the errors
in sector may exceed the capacity of correction logic and some data might be miscorrected.
5.4.6 Real Time EDC Checking
If real time EDC checking logic is enabled by setting RTEDC (0Ah.w6) high, the remainder of serial
data is calculated while the sector is being buffered into DRAM. The sector ready interrupt flag SRIb
(01h.r5) is immediately activated at next sync if the resultant remainder is zero, i.e., no EDC error. If
there is error, the specified error correction is then applied to the buffered data. This function should
not be enabled in disk-monitor mode.
5.4.7 Decoding Sequence Model
DSP data
Sync Dectector
Descrambler
Real Time EDC
Checker
CRCOK?
no
Parrllel ECC
Corrector
EDC Checker
no
CRCOK?
no
Repeat
Correction
Counter = 0
yes
yes
SRIb(01h.5) = 0
yes
5.4.8 Disc Format Selection
Before enable decoder logic through register CTRL0 (0Ah,w), appropriate value should be set to
register CTRL1 (0Bh.w) according to different disc format. If ACEN (0Ah.w4) and M2RQ (0Bh.w3)
are both high, the type of error correction is automatically determined by FORM bit in the subheader
byte rather than setting of F2RQ (0Bh.w2). The value of ACEN (0Ah.w4) does not affect the yellow-
book mode-1 correction.
- 88 -
Publication Release Date: Mar. 1999
Revision 0.61