W88113C Datasheet, PDF (39/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
Bit 0: UDMA - Ultra DMA Enable
Setting this bit high selects data transfer protocol as Ultra DMA. The bandwidth of Ultra DMA
depends on the system frequency and the setting of UDT1-0 (8Ah.5-4).
HICTL0 (1Fh,w)
data-in
data-out
PIO mode
xCh
xEh
MDMA mode
x8h
xAh
UDMA mode
x9h
xBh
STAT5 - Status Register 5 - (read 1Fh)
Bit 7: UTBY - Microprocessor to RAM Transfer Busy
When the microprocessor-to-RAM transfer is not complete, this bit is high.
Bit 6-4: Reserved
Bit 3: MDMA - Multi-word DMA mode
Bit 2: PIO - PIO/DMA mode select
Bit 1: DINB - Data-In Transfer Enable
Bit 0: UDMA - Ultra DMA Enable
HICTL1 - Host Interface Control Register - (write/read 20h)
The value in this register is 26h after chip reset.
Bit 7 : reserved
Bit 6: PDIAGEN - Pin PDIAGb Enable
Setting this bit high causes pin PDIAGb to the active-low state. PDIAGEN is automatically
de-activated, causing pin PDIAGb to be high-impedance, by the following events:
• Reception of Execute Drive Diagnostics Command (ATA opcode 90h)
• Reception of ATA Soft Reset (SRST)
• Chip reset or Host reset
Bit 5: DASPEN - Pin DASPb Enable
Setting this bit high activates pin DASPb. DASPEN is automatically de-activated, causing pin
DASPb to be high-impedance, by the following events:
• Reception of Execute Drive Diagnostics Command (ATA opcode 90h)
• Reception of ATA Soft Reset (SRST)
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Publication Release Date: Mar. 1999
Revision 0.61