W88113C Datasheet, PDF (40/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
• Chip reset or Host reset
This bit is also controlled by DASPS2 (3Fh.2), DASPS1 (3Fh.1) and DASPSS (3Fh.0).
Bit 4: CLRBSY - Clear BSY
Setting this bit high causes the flag BSY in the ATAPI Status Register to become low if APKT
(30h.r0) is not high. This bit is self-clear after the BSY is clear.
Bit 3: SETBSY - Set BSY
Setting this bit high causes the flag BSY in the ATAPI Status Register to become high if
APKT (30h.r0) is not high. This bit is self-clear after the BSY is set.
Bit 2: SCoD - Select Command-Packet-FIFO or Data
The data received from ATAPI Data port is stored in Packet FIFO if this bit is high. This bit is
also controlled by ADTT (17h.w2) and APKTEN (18h.7).
Bit 1: RDYEN - Pin IORDY Enable
Setting this bit high enables IORDY (pin 49) to work with HRDb (pin 50).
Bit 0: IO16EN - Pin IOCS16b Enable
Setting this bit high allows pin IOCS16b to become active-low when 16-bit data access is in
use. This bit should be enabled in normal operation.
SICTL0 - Subcode Interface Control Register 0- (write 21h)
Bit 7-4: Reserved
Bit 3: PQENB - P-data or Q-data Enable
Bits 7 and 6 of subcode data are written to the external RAM if this bit is low.
Bit 2-0: SUBCS[2:0] - Subcode Clock Select
These bits are used to select subcode clock rate.
SUBCS[2:0]
Disk Speed
Subcode Block
Rate
0
1 fold
75 sectors/sec
1
2 fold
150 sectors/sec
2
4 fold
300 sectors/sec
3
-
reserved
4
6 fold
450 sectors/sec
5
8 fold
600 sectors/sec
6
-
reserved
7
-
reserved
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Publication Release Date: Mar. 1999
Revision 0.61