W88113C Datasheet, PDF (53/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
ASERR - ATAPI Shadow Error Register - (write 39h)
Bit 2: SABRT - Shadow ABRT Bit
The microprocessor should set SABRT following each host write to ATCMD to comply with
ATAPI specification if configured as a master drive. The other bits of Shadow Error Register
are all 0s..
LDDBL/LDDBH - Latched Decoded Data Block Register - (read 3Ah/3Bh)
The decoded data block number in DDBH/L is latched into LDDBH/L at the end of EDC check. This
number is available to the end of next EDC check. The LDDBH/L shoule not be used if BICEN
(9Ah.7) is enabled.
APKSTA - Status Register for Automatic Packet Transfer - (write 3Dh)
Bit 4: ADSC - Disk Seek Complete for Automatic Packet Transfer
The value of ADSC is the value of bit DSC in ATAPI Status Register during Automatic Packet
Command Transfers.
ASCSTA - Status Register for Automatic Status Completion - (write 3Eh)
Bit 6: ADRDY - Drive Ready for Automatic Status Completion
The value of ADRDY is the value of bit DRDY in the ATAPI Status Register during Automatic
Status Completion.
Bit 2: ACORR - Correctable Error for Automatic Status Completion
The value of ACORR is the value of bit CORR in the ATAPI Status Register during Automatic
Status Completion. CORR is de-activated by chip reset, host reset, or firmware reset.
Bit 0: ACHECK - Check for Automatic Status Completion
The value of ACHECK is the value of bit CHECK in the ATAPI Status Register during
Automatic Status Completion. CHECK is de-activated by chip reset, host reset, or firmware
reset.
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Publication Release Date: Mar. 1999
Revision 0.61