W88113C Datasheet, PDF (34/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
Writing any value to register TACK (07h) deactivates APKT, TENDb, and corresponding
interrupt.
Bit 6: ADCEN - Automatic DRQ Clearing Enable
When this bit is high, DRQ (37h.3) is cleared to 0 and BSY (37h.7) is set to 1 after the end of
following transfers:
• Host reads from external RAM
• Host writes to Command Packet FIFO
Bit 5: ASCEN - Automatic Status Completion Enable
When this bit is high, Status Completion is performed after the end of the following transfers:
• Host reads from external RAM
• Host writes to Command Packet FIFO
ADCEN (18h.6) should be enabled when ASCEN is enabled to provide clearing of DRQ
(37h.3) and setting of BSY (37h.7). If both ADCEN and ASCEN are enabled, the following
hardware sequence is executed at the end of one of the above data transfers:
• Set BSY
• DRQ (37h.3) ← 0
• CHECK (37h.0) ← ACHECK (3Eh.0)
• CORR (37h.2) ← ACORR (3Eh.2)
• DRDY
(37h.6) ← ADRDY (3Eh.6)
• ATINT (32h) ← 03h
• Clear BSY
• HIRQ (2Eh.3) ← 1
• APKTEN (18h.7) ← 1, if AUTOEN (18h.4) is high
• ASCEN (18h.5) ← 0
After detecting the interrupt, the host reads the ATAPI Status Register and if necessary, the
Error Register for the command completion status.
Bit 4: AUTOEN - Automatic APKTEN Set After Status Completion Enable
When this bit is high, APKTEN (18h.7) will be set after Automatic Status Completion
sequence triggered by either SCT (17h.0) or ASCEN (18h.5).
Bit 3: STWCEN - Set Transfer Word Count Enable
When this bit is high, the value (TWCH/L + 1) × 2 is loaded into ATBLO and ATBHI when
ADTT (17h.2) is triggered and PIO (1Fh.2) has been set high. If ACMEN (9Ch.6) is not
enabled, control bit STWCEN should not be set for Multiple Block Transfer. Instead,
ATBHI/LO should be set by firmware to: (MBC4-0 + 1) × (TWCH/L + 1) x 2.
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Publication Release Date: Mar. 1999
Revision 0.61