W88113C Datasheet, PDF (54/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
SHDCTL - Shadow Drive Control Register (read/write 3Fh)
Bit 7, 4, 3: Reserved
Bit 6: SHDRV - Shadow Drive Enable
If MDRV (2Fh.4) is high, the bit reflects the level on pin DASPb (43) until SHDRVL (3Fh.5) is
set high. If this bit is high, Shadow Register support for the non-existent Slave Drive is
enabled..
Bit 5: SHDRVL - Shadow Drive Enable Latch
Microprocessor should set this bit high at least 450 milliseconds after chip reset or host reset
to latch the setting of SHDRV (3Fh.6) from pin DASPb if configured as a master drive. This
bit is 0 after chip reset and host reset.
Bit 2: DASPS2 - DASP Select 2
Setting this bit high enables DASPEN (20h.w5) during host reset. DASPS2 should normally
be 0 to comply with ATAPI specification. This bit is 0 after chip reset.
Bit 1: DASPS1 - DASP Select 1
Setting this bit high enables DASPEN (20h.w5) following end of host reset. This bit is 0 after
chip reset.
Bit 0: DASPSS - DASP SRST Select
Setting this bit high enables DASPEN (20h.w5) following the end of soft reset (SRST). This
bit is 0 after chip reset and host reset.
LSTA0 to LSTA3 - Latched Status Registers - (read 48h to 4Bh)
The contents of STAT0-3 (0C-0Fh,r) are latched into these four registers at the end of EDC check.
These values are available to the end of next EDC check. These registers shoule not be used if
BICEN (9Ah.7) is enabled.
LHD0 to LHD3 - Latched Header Registers - (read 4Ch to 4Fh)
The contents of HEAD0-3 (04-07h.r) are latched into these four registers at the end of EDC check.
These values are available to the end of next EDC check. These registers shoule not be used if
BICEN (9Ah.7) is enabled.
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Publication Release Date: Mar. 1999
Revision 0.61