W88113C Datasheet, PDF (43/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
Bit 5: Reserved (write only)
Bit 4: SWAP - Host High-Low Swap
Setting this bit high causes the host access of high/low byte to be swapped.
Bit 3: Reserved
Bit 2-0: RTC[2:0] - External RAM Type Configuration Bits
The external RAM should be appropriately configured by these three bits according to its
specification. RTC[2:0] are de-activated by chip reset or host reset, but are not changed by
firmware reset.
RTC[2:0]
RAM Configuration
0,1, 4, 7
reserved
2
256K x 4-bit x 2, 256K x 8-bit x 1,
128K x 8-bit x 1, 8-Row 9-Column
3
128K x 8-bit x 1, 9-Row 8-Column
4
64K x 16-bit x 1, (8-row 8-Column)
128K x 16-bit x 1 (9-Row 8-Column)
128K x 8-bit x 2 (9-Row 8-Column)
5
256K x 16-bit x 1
128K x 16-bit x 1 (8-Row 9-Column)
128K x 8-bit x 2, (8-Row 9-Column)
6
1 M x 4-bit x 2
Note: The control bit ALE2 (5Ch.3) must be set while using 16-bit DRAM.
MEMCF - Memory Layout Configuration Register - (write 2Bh)
Bits 7-6: Reserved
Bits 5-4: DBAF[1:0] - DRAM Bus Arbitration Factor
The value in control bits DBAF1-0 (2Bh.w5-4) defines the DRAM bus arbitration factor, daf,
which can adjust the number of cycles between two host transfer pre-fetch cycles is at most
2^daf. If less bandwidth is demanded by logic other than host transfer, the bandwidth is
automatically arbitrated to achieve the best performance. If The value in these bits is 0 after
chip reset and firmware reset.
Bit 3: DFRST - Data FIFO Reset
Setting this bit high resets Data FIFO. This bit is not self-clear.
Bit 2: FRDY - Fast Pin IORDY Enable
Setting this bit high accelerates the de-assertion of pin IORDY (49) without referring pin
HRDb (50).
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Publication Release Date: Mar. 1999
Revision 0.61