W88113C Datasheet, PDF (46/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
MISS0 - Miscellaneous Status Register 0 - (read 2Eh)
Bit 5: SRUb - Status Register Updated Flag
This bit becomes high when the ATAPI Status Register is updated by the following:
• Microprocessor writes to 37h
• Microprocessor triggers DSCT (17h.w5)
• Microprocessor triggers SCT (17h.w0)
• Automatic Status Completion occurs if ASCEN (18h.5) is enabled
• Reception of A0h command if APKTEN (18h.7) is enabled
• Chip reset or host reset
Bit 4: MDRVF - Master Drive Flag
This bit is high if the drive is configured as Master. This bit is low if the drive is configured as
Slave.
Bit 3: HINTF - Host Interrupt Flag
This bit reflects the status of the source of pin HIRQ (47).
Bit 2: nIEN - Bit nIEN in Device Control Register
This bit reflects the value of bit nIEN in ATAPI Device Control Register.
Bit 1: PDIAGb - Pin PDIAGb Flag
This bit reflects the status of pin PDIAGb (43).
Bit 0: DASPb - Pin DASPb Flag
This bit reflects the status of pin DASPb (37).
MISC1 - Miscellaneous Control Register 1 - (write 2Fh)
This register is 0 after chip reset.
Bit 7: ARRC - ATAPI Register Read Control
When this bit is high, the ATAPI registers can be read regardless of the value of BSY if the
drive is selected.
Bit 6: SARRC - Shadow Drive ATAPI Register Read Control
When this bit is high, the Shadow ATAPI registers can be read regardless of the value of BSY
if the shadow drive is selected.
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Publication Release Date: Mar. 1999
Revision 0.61