W88113C Datasheet, PDF (57/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
Bit 6: ASRIT - Alternate SRIb Timing (obsolete function)
Bit 5: DSP1STB
Bit 4: reserved
Bit 3: ALRT - Alternate Latch Registers Timing (obsolete function)
Bit 2: Reserved
Bit 1: DRA - Direct Register Addressing Enable
If this bit is set high, the Direct Register Addressing function is enabled. This bit is 1 after
chip reset in normal condition. But if pin RA8 (92) is connected to a 4.7KΩ pull-down resister,
this bit is set high after chip reset. This alternative power-on setting provides a way to do
conventional indirect register addressing.
Bit 0: Reserved
Power-On Setting of Register Addressing Mode
The default register addressing mode of W88113CF is direct register addressing mode.
Alternative Power-On Setting
RA8 pull-down RA7 pull-down Direct Register ALE input pin 16-bit DRAM
4.7KΩ
4.7KΩ
Select
support
no (default)
no (default)
yes
ALE2
yes
no
yes
yes
ALE1
no
yes
no
no
x
yes
yes
yes
no
x
no
EFCTL2 - Enhanced Feature Control Register 2- (read/write 5Ch)
Bit 7-4: Reserved
Bit 3: ALE2 - ALE2 Enable
When this bit is set high, pin ALE2 (64) is used as ALE input. This bit is 1 after chip reset in
normal condition. But if pin RA7 (93) is connected to a 4.7KΩ pull-low resister, this bit is set
low after chip reset.
Bit 2: SYNCP - Sync Bytes Patch Enable
If this bit is high, the sync bytes of the following sector are patched to the previous sector.
This bit must be disabled when reading CD-DA data.
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Publication Release Date: Mar. 1999
Revision 0.61