W88113C Datasheet, PDF (10/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
Audio Interface
NAME
ABCK
CLKO/ALRCK
ACLK
ASD0
ROEB/ASD1
RD8/ASD2
NO.
6
13
46
58
84
86
TYPE
O
O
I
O
O
O
PIN DESCRIPTION
Audio Bit Clock
Audio Left/Right Clock
Audio Reference Clock
Audio Serial Data 0
Audio Serial Data 1
Audio Serial Data 2
Host Interface
NAME
DD[15:0]
DA[2:0]
DASPb
CS3b
CS1b
PDIAGb
CS16b
HIRQ
DMACKb
IORDY
HRDb
HWRb
DMARQ
NO.
54, 56, 59, 62,
65, 68, 70, 73,
74, 71, 69, 67,
63, 61, 57, 55
40, 44, 42
37
TYPE
I/OZ
I
I/OD
38
I
39
I
43
I/OD
45
OD
47
OZ
48
I
49
OZ
50
I
52
I
53
OZ
PIN DESCRIPTION
Host Data Bus - Signals enable data transfer between the host
and W88113A.
Host Address Bus - Signals to access various ATAPI registers.
Drive Active/Drive 1 Present - A time-multiplexed signal
indicating whether a drive is active, or Drive 1 is present.
Host Chip Select 1 - A low-active input signal used to select the
host Control Block Registers.
Host Chip Select 0 - A low-active input signal used to select the
host Command Block Registers.
Passed Diagnostics - A signal asserted by Drive 1 to indicate to
Drive 0 that diagnostic is completed.
16-bit I/O Select - A low-active output signal to indicate a 16-bit
data transfer.
Host Interrupt - A signal to request an interrupt service from
host.
DMA Acknowledge - A low-active input signal used for DMA
transfer by the host when DMARQ is ready.
I/O Channel Ready - When device is not ready for a data
transfer request, this signal is negated for extension of the host
data transfer cycle within any host register access.
Host I/O Read - A low-active read strobe signal.
Host I/O Write - A low-active write strobe signal.
DMA Request - A high-active signal asserted for DMA data
transfer when device is ready to transfer data to or from the
host.
Publication Release Date: Mar. 1999
-6-
Revision 0.61