W88113C Datasheet, PDF (23/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
DECEN BUFEN EDCEN QCEN PCEN
0Ah.7 0Ah.2 0Ah.5 0Ah.1 0Ah.0
Decoder
Mode
Operation
Flow
1
1
1
1
1
Q-P correction Q → P → CRC
1
1
1
1
0
Q-correction
Q → CRC
1
1
1
0
1 P-correction
P → CRC
1
1
1
0
0 Buffer-only
CRC
1
0
0
0
0
Disk-monitor
no buffering
0
X
X
X
X Decoder
disable
no operation
Note that if ATMSEN (9Ah.6) is high, the decoder logic will operate in Disk-monitor mode before the
target is found. When the target is found, the setting of register CTRL1 (0Bh,w) will be automatically
loaded into decoder logic.
CTRL1 - Control Register 1 - (write 0Bh)
This register is 0 after chip reset, host reset, firmware reset and decoder reset.
Bit 7: SIEN - Sync Insertion Enable
When this bit is high, the sector boundary is determined by internal sync insertion logic.
Bit 6: SDEN - Sync Detection Enable
When this bit is high, the sector boundary is determined by sync bytes of incoming serial
data. This bit should not set for reading CD-DA data.
Bit 5: DSCREN - Descrambler Enable
Setting this bit is high enables the descramble logic. This bit should not set for reading CD-
DA data.
Bit 4: CWEN - Corrected Data Write Enable
Setting this bit high enables corrected data to be written to the external RAM. This bit is
normally set when correction is enabled by QCEN (0Ah.w1) or PCEN (0AH.w0).
Bit 3: M2RQ - Mode 2 ECC Request
Setting this bit to high enables the CD-ROM XA mode 2 correction logic. Yellow book Mode
1 correction will be performed if this bit is low.
Bit 2: F2RQ - Form 2 Request
Setting this bit high request the data to be processed by the CD-ROM XA mode-2 form-2
format if M2RQ (0Bh.3) is high. If M2RQ (0Bh.3) is high and this bit is low, the CD-ROM X1
mode-2 form-1 correction will be performed. This bit is not effective if ACEN (0Ah.w4) is
high.
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Publication Release Date: Mar. 1999
Revision 0.61