W88113C Datasheet, PDF (37/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
DSPSL - DSP Selection Register - (write 1Bh)
Bit 7: C2ML - C2 MSB to LSB
When this bit is high, the sequence of erasures via pin C2PO (11) is from MSB to LSB.
Bit 6: S16O - Select 16 Offset
The incoming serial data is latched one clock after pin LRCK (13) changes if this bit is high.
Bit 5: LCHP - Left Channel Polarity
The incoming serial data is latched as left channel when pin LRCK (13) is high if this bit is
high.
Bit 4: SFT8 - Shift 8 Clocks
The incoming serial data is latched by delay 8 clocks if this bit is high.
Bit 3: Reserved
Bit 2: SEL16 - Select 16 Bits Per Channel
The incoming serial data is latched 16 times per channel if this bit is high.
Bit 1: DIR - Data Direction
Setting this bit high selects the direction of data from pin SDATA (9) from MSB to LSB.
Bit 0: EDGE - Latching Edge Select
Setting this bit high selects the rising edge of BCK for latching data from pin SDATA (9).
DSP setting example:
DSPSL
DSP Data Format
07h
Toshiba
24h
Sanyo
A3h
Sony 48-bit slot
C3h
Philip
C2BEB - C2 Block Error Byte - (read 1Bh)
The Block Error Byte is the OR of all the C2 Error Flag bytes.
RACL, RACH, and RACU - RAM Address Counter - (write 1Ch, 1Dh, 2Dh)
These three registers are used to set linear address of the external RAM. Before accessing registers
RAMRD/RAMWR or triggering linear-address transfer, microprocessor should set these registers.
The microprocessor should write the RAM starting address into the counter while busy flag UTBY
(1Fh.r7) is low. Then this counter increases automatically each time when a byte is read or written.
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Publication Release Date: Mar. 1999
Revision 0.61