W6692 Datasheet, PDF (93/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
A "1" enables W6692 to assert PME#. When "0", PME# assertion is disabled. If the PME# is active, writing "0" to this bit also
clears the PME# signal.
Bits 7-2 Reserved
These bits are reserved and read as 0.
Bits 1-0 Power State Read/Write
Used to get or set the device's power state.
00b - D0: fully operational
01b - D1: Not responds to PCI IO and memory accesses (PCI transation may or may not present, bus clock and VCC present),
only responds to PCI configuration access, B2 HDLC stopped
10b - D2: Not responds to PCI IO and memory accesses (PCI transation may or may not present, bus clock may or may not
present, VCC present), only responds to PCI configuration access, B1 and B2 HDLCs stopped
11b - D3_hot : only responds to PCI configuration access accesses (PCI transation may or may not present, bus clock may or
may not present, VCC may or may not present, 3.3Vaux present), a soft reset is performed when returns to D0
Note 1: In D3cold state, PCI RST# is active and the PME#-related circuit must not be blocked by RST# signal.
Note 2: When PCI bus recovers from B3 to B0, W6692 must be able to accept IO or memory access in less than 10 ms.
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Publication Release Date: Sep 30, 1999
Revision 0.9