W6692 Datasheet, PDF (45/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
command too. The microprocessor indicates the end of the frame transmission by issuing XME (Transmit Message End) and
XMS commands at the same time. The transmitter then transmits all the data left in the transmit FIFO and appends the CRC and
closing flag. After this, a XFR interrupt is generated.
The inter-frame time fill pattern can be programmed to 1's or flags.
During the frame transmission, the microprocessor reaction time for the XFR interrupt depends on the FIFO threshold setting
and B channel data rate. For example, it is 8 ms if the FIFO threshold is 64 and the B channel data rate is 64 kbps. If the
microprocessor fails to responds within the given reaction time, the transmit FIFO will be underrun. In this case, the W6692 will
automatically reset the transmitter and send the inter frame time fill pattern on B channel. The microprocessor is informed about
this via a Transmit Data Underrun interrupt (XDUN bit in Bn_EXIR register). The microprocessor must wait until transmit FIFO
ready (via XFR interrupt), re-write data, and issue XMS command to re-transmit the data.
The microprocessor can abort a frame transmission by issuing a Transmitter Reset command (XRES bit in Bn_CMDR
register). The XRES command resets the transmitter and sends inter frame time fill pattern on B channel. It also results in a
transmit pool ready condition.
Extended transparent mode:
All the data in the transmit FIFO are transmitted without any modification, i.e. no flags and CRCs are inserted, and no bit
stuffing is performed.
Transmission is started by a XMS command. The transmitter requests another block of data via XFR interrupt when more than
a threshold length of vacancies are left in the FIFO. The microprocessor reacts to this condition by writing up to a threshold
length of data into the transmit FIFO and issues a XMS command to continue the message transmission.
The microprocessor reaction time depends on the FIFO threshold setting and B channel data rate. For example, it is 8 ms if the
FIFO threshold is 64 and the B channel data rate is 64 kbps. If the microprocessor fails to respond within the given reaction time,
the transmit FIFO will hold no data to transmit. In this case, the W6692 will automatically reset the transmitter and send idle
channel pattern defined in Bn_IDLE register. The microprocessor is informed about this via a Transmit Data Underrun interrupt
(XDUN bit in Bn_EXIR register). The microprocessor must wait until transmit FIFO ready (via XFR interrupt), re-write data,
and issue XMS command to re-transmit the data.
7.8 GCI Mode Serial Interface Bus
The GCI is a generalization and enchancement of the general purpose, serial interface bus. The GCI bus offers capacity for the
transfer of maintenance information. In terminal applications, the GCI constitute a powerful backplane bus offering
sophisticated control capabilities for peripheral modules. The channel structure of the GCI mode is depicted below:
Channel Structure of the W6692 GCI Mode:
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Publication Release Date: Sep 30, 1999
Revision 0.9