W6692 Datasheet, PDF (88/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
PCI Configuration Address: 0C_H
Default: 0000 0000 _H
W6692 PCI ISDN S/T-Controller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BIST
Header Type
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Latency Timer
Cache Line Size
Bits 31-24 BIST Built-in Self Test Read_only
This register is always read as 0. It means that W6692 does not support BIST function.
Bits 23-16 Header Type Read_only
The value of this register is 00_H. This means a signle function device, with header type 00_H.
Bits 15-8 Latency Timer Read_only
This register is not implemented and is read as 0.
Bits 7-0 Cache Line Size Read_only
This register is not implemented and is read as 0.
8.4.5 Base Address Register 0
Read/Write
Address 10_H
Depending on EEPROM status and MEN, IEN bits in EEPROM, there are different implementations:
MEN IEN
1
1
1
0
0
1
0
0
EEPROM empty
Location 10H
Memory Base Address Reg.
Memory Base Address Reg.
IO Base Address Reg.
Not Implemented
Memory Base Address Reg.
Location 14H
IO Base Address Reg.
Not Implemented
Not Implemented
Not Implemented
IO Base Address Reg.
PRE used
Yes
Yes
No
No
PRE=0
If EEPROM is empty, the power on reset value at 10_H =0000 0000_H, and the power on reset value at 14_H =0000 0001_H
Memory Base Adress Register:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Memory Base Address
15 14 13 12 11 10 9
8
7
6
5
4
3
21
0
Memory Base Address
Hardwired to 0
PRE
Type
0
This register can be used to relocate memory address space to any location that is aligned to 4K bytes for mapping W6692's
internal registers.
Bits 31-12 Memory Base Address R/W
-88 -
Publication Release Date: Sep 30, 1999
Revision 0.9