W6692 Datasheet, PDF (4/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
7.6.2 Reception of Frames in D Channel..............................................................................................................................41
7.6.3 Transmission of Frames in D Channel ........................................................................................................................42
7.7 B Channel HDLC Controller ..........................................................................................................................................43
7.7.1 Reception of Frames in B Channel .........................................................................................................................43
7.7.2 Transmission of Frames in B Channel ........................................................................................................................44
7.8 GCI Mode Serial Interface Bus.......................................................................................................................................45
7.8.1 GCI Mode C/I0 Channel Handling..............................................................................................................................46
7.8.2 GCI Mode Monitor Channel Handling........................................................................................................................46
7.9 PCI/MP Interface Circuit................................................................................................................................................48
7.9.1 PCI Slave Mode And Configuration Serial EEPROM .................................................................................................48
7.9.2 8-bit Microprocessor Interface.....................................................................................................................................49
7.10 Peripheral Control.........................................................................................................................................................49
8. REGISTER DESCRIPTIONS ......................................................................................................51
8.1 Chip Control and D_ch HDLC controller ......................................................................................................................51
8.1.1 D_ch receive FIFO D_RFIFO Read Address 00H/00H ...........................................................................................53
8.1.2 D_ch transmit FIFO D_XFIFO Write Address 04H/01H.........................................................................................53
8.1.3 D_ch command register D_CMDR Read/Write Address 08H/02H ...........................................................................54
8.1.4 D_ch Mode Register D_MODE Read/Write Address 0CH/03H................................................................................54
8.1.5 Timer 1 Register TIMR1 Read/Write Address 10H/04H ........................................................................................55
8.1.6 Interrupt Status Register ISTA Read_clear Address 14H/05H.............................................................................56
8.1.7 Interrupt Mask Register IMASK R/W Address 18H/06H..........................................................................................57
8.1.8 D_ch Extended Interrupt Register D_EXIR Read_clear Address 1CH ......................................................................57
8.1.9 D_ch Extended Interrupt Mask Register D_EXIM Read/Write Address 20H/08H ....................................................58
8.1.10 D_ch Status Register D_XSTA Read Address 24H/09H .....................................................................................58
8.1.11 D_ch Receive Status Register D_RSTA Read Address 28H/0AH .........................................................................59
8.1.12 D_ch SAPI Address Mask D_SAM Read/Write Address 2CH/0BH......................................................................59
8.1.13 D_ch SAPI1 Register D_SAP1 Read/Write Address 30H/0CH .............................................................................60
8.1.14 D_ch SAPI2 Register D_SAP2 Read/Write Address 34H/0DH...............................................................................60
8.1.15 D_ch TEI Address Mask D_TAM Read/Write Address 38H/0EH .........................................................................60
8.1.16 D_ch TEI1 Register D_TEI1 Read/Write Address 3CH/0FH................................................................................61
8.1.17 D_ch TEI2 Register D_TEI2 Read/Write Address 40H/10H ................................................................................61
8.1.18 D_ch Receive Frame Byte Count High D_RBCH Read Address 44H/11H............................................................61
8.1.19 D_ch Receive Frame Byte Count Low D_RBCL Read Address 48H/12H.............................................................62
8.1.20 Timer 2 TIMR2
Write Address 4CH/13H..........................................................................................62
8.1.21 Layer 1_Ready Code L1_RC
Read/Write Address 50H/14H ...............................................................62
8.1.22 Control Register CTL Read/Write Address 54H/15H .............................................................................................63
8.1.23 Command/Indication Receive Register CIR Read Address 58H/16H ....................................................................63
8.1.24 Command/Indication Transmit Register CIX Read/Write Address 5CH/17H........................................................64
8.1.25 S/Q Channel Receive Register SQR Read Address 60H/18H..............................................................................64
8.1.26 S/Q Channel Transmit Register SQX Read/Write Address 64H/19H ..................................................................65
8.1.27 Peripheral Control Register PCTL Read/Write Address 68H/1AH ....................................................................65
8.1.28 Monitor Receive Channel 0 MO0R Read Address 6CH/1BH ............................................................................66
8.1.29 Monitor Transmit Channel 0 MO0X Read/Write Address 70H/1CH .................................................................67
8.1.30 Monitor Channel 0 Interrupt Register MO0I Read_clear Address 74H/1DH......................................................67
8.1.31 Monitor Channel 0 Control Register MO0C Read/Write Address 78H/1EH..........................................................67
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Publication Release Date: Sep 30, 1999
Revision 0.9