W6692 Datasheet, PDF (57/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
D_EXI D_ch Extended Interrupt
This bit indicates that at least one interrupt bit has been set in D_EXIR register.
B1_EXI B1_ch Extended Interrupt
This bit indicates that at least one interrupt bit has been set in B1_EXIR register.
B2_EXI B2_ch Extended Interrupt
This bit indicates that at least one interrupt bit has been set in B2_EXIR register.
Note : A read of the ISTA register clears all bits except D_EXI, B1_EXI and B2_EXI bits. D_EXI bit is cleared when all bits
in D_EXIR register are cleared. B1_EXI bit is cleared by reading B1_EXI register and B2_EXI bit is cleared by reading
B2_EXIR register.
8.1.7 Interrupt Mask Register IMASK R/W Address 18H/06H
Value after reset: FFH
7
6
5
D_RMR D_RME D_XFR
4
XINT1
3
XINT0
2
1
0
D_EXI B1_EXI B2_EXI
Setting the bit to "1" masks the corresponding interrupt source in ISTA register. Masked interrupt status bits are read as zero.
They are internally stored and pending until the mask bits are zero.
Setting the D_EXI, B1_EXI or B2_EXI bit to "1" masks all the interrupts in D_EXIR, B1_EXIR or B2_EXIR register,
respectively.
8.1.8 D_ch Extended Interrupt Register D_EXIR Read_clear Address 1CH
Value after reset: 00H
7
6
5
4
3
2
1
0
RDOV XDUN XCOL TIN2 GCI ISC T1EXP 0
RDOV Receive Data Overflow
Frame overflow (too many short frames) or data overflow occurs in the receive FIFO. In data overflow, the incoming data will
overwrite the data in the receive FIFO. If RDOV interrupt occurs, software has to reset the receiver and discard the data received.
XDUN Transmit Data Underrun
This interrupt indicates the D_XFIFO has run out of data. In this case, the W6692 will automatically reset the transmitter and
send the inter frame time fill pattern (all 1's) on D channel. The microprocessor must wait until transmit FIFO ready (via XFR
interrupt), re-write data, and issue XMS command to re-transmit the data.
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Publication Release Date: Sep 30, 1999
Revision 0.9