W6692 Datasheet, PDF (74/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
Transmit data of GCI IC2 channel. A read to this register returns the previously written value.
8.1.44 GCI CI1 Indication Register
CI1R
Read
Address 7DH/48H
Value after reset : Undefined
7
6
5
4
3
2
1
0
CI1R_6 CI1R_5 CI1R_4 CI1R_3 CI1R_2 CI1R_1
MR
MX
CI1R_6-0
Input data of GCI CI1 channel.
Example application is data of ARCOFI's Peripheral Control Interface input pins.
8.1.45 GCI CI1 Command Register
CI1X
Read/Write
Value after reset: FFH
7
6
5
4
3
2
1
0
CI1X_6 CI1X_5 CI1X_4 CI1X_3 CI1X_2 CI1X_1 MR
MX
CI1X6_0
Transmitted data of GCI CI1 channel. A read to these bits returns the previously written value.
Example application is data of ARCOFI's Peripheral Control Interface output pins.
Address 7EH/49H
8.1.46 GCI Extended Interrupt Register GCI_EXIR Read_clear Address 76H/4AH
Value after reset : 00H
7
6
5
4
3
2
1
0
0
0
0
MO1C MO0C IC1
IC2
CI1
MO1C Monitor Channel 1 Status Change
A change in the Monitor Channel 1 Interrupt register ( MO1I ) has occurred. A new Monitor channel byte is stored in the
MO1R register.
MO0C Monitor Channel 0 Status Change
A change in the Monitor Channel 0 Interrupt register (MO0I) has occurred. A new Monitor channel byte is stored in the MO0R
register.
IC1 IC1 Synchronous Transfer Interrupt
When enabled, an interrupt is generated at end of GCI IC1 transfer every GCI frame (125 µs).
IC2 IC2 Synchronous Transfer Interrupt
When enabled, an interrupt is generated at end of GCI IC2 transfer every GCI frame (125 µs).
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Publication Release Date: Sep 30, 1999
Revision 0.9