W6692 Datasheet, PDF (58/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
XCOL Transmit Collision
This bit indicates a collision on the S-bus has been detected. A XRST command must be issued and software must wait until
transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS command to re-transmit the data.
TIN2 Timer 2 Expiration
This bit is set when Timer 2 counts down to zero.
GCI GCI Interrupt
This bit is set when at least one bit is set in GCI_EXIR register.
ISC Indication or S Channel Change
A change in the layer 1 indication code or multiframe S channel has been detected. The actual value can be read from CIR or
SQR registers.
T1EXP Timer 1 Expiration
Expiration occurs in the Timer 1.
.
8.1.9 D_ch Extended Interrupt Mask Register D_EXIM
Read/Write Address 20H/08H
Value after reset: FFH
7
6
5
4
3
2
1
0
RDOV XDUN XCOL TIN2 GCI ISC T1EXP 1
Setting the bit to "1" masks the corresponding interrupt source in D_EXIR register. Masked interrupt status bits are read as
zero. They are internally stored and pending until the mask bits are zero.
All the interrupts in D_EXIR will be masked if the IMASK:D_EXI bit is set to "1".
8.1.10 D_ch Status Register
D_XSTA Read
Address 24H/09H
Value after reset: 00H
7
6
5
4
3
2
1
0
XDOW
XBZ DRDY
XDOW Transmit Data Overwritten
At least one byte of data has been overwritten in the D_XFIFO. This bit is set by data overwritten condition and is cleared only
by XRST command.
XBZ Transmitter Busy
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Publication Release Date: Sep 30, 1999
Revision 0.9