W6692 Datasheet, PDF (5/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
8.1.32 GCI Mode Control/Status Register GCR
Read/Write Address 7CH/1FH.......................................68
8.1.33 Peripheral Address Register XADDR Read/Write Address F4H/3DH ...............................................................69
8.1.34 Peripheral Data Register XDATA Read/Write Address F8H/3EH.....................................................................70
8.1.35 Serial EEPROM Control Register EPCTL Read/Write Address FCH/3FH ............................................................71
8.1.36 Monitor Receive Channel 1 Register MO1R Read Address 6DH/40H .................................................................71
8.1.37 Monitor Transmit Channel 1 MO1X Read/Write Address 71H/41H..................................................................72
8.1.38 Monitor Channel 1 Interrupt Register MO1I Read_clear Address 75H/42H ......................................................72
8.1.39 Monitor Channel 1 Control Register MO1C Read/Write Address 79H/43H ..........................................................72
8.1.40 GCI IC1 Receive Register IC1R Read Address 6EH/44H................................................................................73
8.1.41 GCI IC1 Transmit Register IC1X Read/Write Address 72H/45H.....................................................................73
8.1.42 GCI IC2 Receive Register IC2R Read Address 6FH/46H ................................................................................73
8.1.43 GCI IC2 Transmit Register IC2X Read/Write Address 73H/47H.....................................................................73
8.1.44 GCI CI1 Indication Register CI1R Read Address 7DH/48H ............................................................................74
8.1.45 GCI CI1 Command Register CI1X Read/Write Address 7EH/49H ..................................................................74
8.1.46 GCI Extended Interrupt Register GCI_EXIR Read_clear Address 76H/4AH ..........................................................74
8.1.47 GCI Extended Interrupt Mask Register GCI_EXIM Read/Write Address 7AH/4BH ...............................................75
8.2 B1 HDLC controler .........................................................................................................................................................75
8.2.1 B1_ch receive FIFO B1_RFIFO Read Address 80H/20H .....................................................................................76
8.2.2 B1_ch transmit FIFO B1_XFIFO Write Address 84H/21H .................................................................................76
8.2.3 B1_ch command register B1_CMDR Read/Write Address 88H/22H....................................................................77
8.2.4 B1_ch Mode Register B1_MODE Read/Write Address 8CH/23H ..........................................................................78
8.2.5 B1_ch Extended Interrupt Register B1_EXIR Read_clear Address 90H/24H............................................................79
8.2.6 B1_ch Extended Interrupt Mask Register B1_EXIM Read/Write Address 94H/25H .................................................80
8.2.7 B1_ch Status Register B1_STAR Read Address 98H/26H......................................................................................80
8.2.8 B1_ch Address Mask Register 1 B1_ADM1 Read/Write Address 9CH/27H...........................................................81
8.2.9 B1_ch Address Mask Register 2 B1_ADM2 Read/Write Address A0H/28H...........................................................81
8.2.10 B1_ch Address Register 1 B1_ADR1 Read/Write Address A4H/29H ...................................................................81
8.2.11 B1_ch Address Register 2 B1_ADR2 Read/Write Address A8H/2AH ..................................................................82
8.2.12 B1_ch Receive Frame Byte Count Low B1_RBCL Read Address ACH/2BH..........................................................82
8.2.13 B1_ch Receive Frame Byte Count High B1_RBCH Read Address B0H/2CH .........................................................82
8.2.14 B1_ch Transmit Idle Pattern B1_IDLE Read/Write Address B4H/2DH ..................................................................83
8.3 B2 HDLC controller ........................................................................................................................................................83
8.4 PCI Configuration Register.............................................................................................................................................84
8.4.1 Device/Vendor ID Register Read Address 00 _H .................................................................................................85
8.4.2 Status/Command Register Read/Write Address 04_H...........................................................................................85
8.4.3 Class Code/Revision ID Register Read Address 08_H ..........................................................................................87
8.4.4 Header Type/Latency Timer Register Read Address 0C_H ....................................................................................87
8.4.5 Base Address Register 0 Read/Write Address 10_H............................................................................................88
8.4.6 Base Address Register 1 Read/Write Address 14_H .............................................................................................89
8.4.7 Subsystem/Subsystem Vendor ID Register Read Address 2C_H...........................................................................89
8.4.8 Interrupt Line Register Read/Write Address 3C_H...............................................................................................90
8.4.9 Capability Pointer Read Address 34_H ................................................................................................................90
8.4.10 Power Management Capability Read Address 40_H ...........................................................................................91
8.4.11 Power Management Control/Status Read/Write Address 44_H ...........................................................................92
9. ELECTRICAL CHARACTERISTICS...........................................................................................94
9.1 Absolute Maximum Rating..............................................................................................................................................94
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Publication Release Date: Sep 30, 1999
Revision 0.9