W6692 Datasheet, PDF (48/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
During a transmission process, it is possible for the receiver to ask a transmission to be aborted by sending an inactive MR bit
value in two consecutive frames. This is effected by the microprocessor writing the MR control bit MRC to 0. An aborted
transmission is indicated by a MAB (Monitor Channel Data Abort) interrupt status at the transmitter.
7.9 PCI/MP Interface Circuit
7.9.1 PCI Slave Mode And Configuration Serial EEPROM
W6692 implements slave (target) mode function which meets PCI local bus specification revision 2.2 and PCI Power
Management 1.1. All the signals are 5V, 33 MHz compatible. A single function, type 00h configuration header is implemented
for control of the internal ISDN device and external peripheral device(s). Memory mode and/or IO mode can be used for W6692's
register access.
After power on reset, W6692 starts to read configuration data from serial EEPROM. The first word read is Vendor ID, if it
equals FFFFH, a EEPROM empty condition is assumed and chip's internal default configuration data is used, otherwise, the
configuration data stored in serial EEPROM is used. The default configuration data is as follows:
Vendor ID
Device ID
Class Code
Revision ID
Interface Code
Subclass Code
Base Class Code
Subsystem Vendor ID
Subsystem ID
Memory Base Address Register
IO Base Address Register
: 1050H (Winbond's ID)
: 6692H
: 02 04 00H
: 00H
: 00H
: 04H
: 02H
: FFFFH
: FFFFH
: Enabled and Implemented at 10H
: Enabled and Implemented at 14H
A 9346/93C46 type serial EEPROM is used for configuration data storage. The EEPORM's data layout is as follows :
Address/Byte
0_H
2_H
4_H
6_H
8_H
A_H
C_H
E_H
1
0
Vendor ID
Device ID
Interface Code
Revision ID
Base Class Code
Subclass Code
Subsystem Vendor ID
Subsystem ID
Address Register Control
PMC
FIG.7.9 SERIAL EEPROM DATA LAYOUT
-48 -
Publication Release Date: Sep 30, 1999
Revision 0.9