W6692 Datasheet, PDF (49/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
Word 6 (Bytes 12,13) is for Address Register Control, its format is :
15
14 13 12
0
MEN IEN PRE
not used
The Address Register Control determines the PCI address register's implementation. Bit 13 is the prefetchable bit in Memory
Base Address register.
MEN IEN
1
1
1
0
0
1
0
0
EEPROM empty
PCI Configuration Space
Location 10H
Memory Base Address Reg.
Memory Base Address Reg.
IO Base Address Reg.
Not Implemented
Memory Base Address Reg.
PCI Configuration Space
Location 14H
IO Base Address Reg.
Not Implemented
Not Implemented
Not Implemented
IO Base Address Reg.
Bit 13
used ?
yes
yes
no
no
PRE=0
In all cases, Memory Base Address register allocates 4096 byte spaces and IO Base Address register allocates 256 byte space.
Word 7 is Power Management Capability register. It replaces the chip's default value if EEPROM is not empty.
W6692 provides an EPCTL register for on-board access of the serial EEPROM. Software is responsible for creation of the serial
EEPROM waveform and timing and can read, write or erase the EEPROM's content.
7.9.2 8-bit Microprocessor Interface
At power up, the reset pin RST# must be asserted to initialize the chip. At rising edge of RST#, data at CLK pin determines the
operation modes: clock for PCI mode, HIGH for Intel bus mode, LOW for Motorola bus mode.
7.10 Peripheral Control
In PCI card with POTS application, the peripheral devices such as CODEC, DTMF and SLIC can be directly controlled by
W6692, therefore eliminates the need for another PCI controller chip. The peripheral control function includes timer, interrupt
inputs and programmable IOs or microprocessor interface.
There are two timers implemented in W6692: TIMR1 and TIMR2. TIMR1 is a long period timer whcich can be used to control
the cadence of ring tone. TIMR2 is a short period timer which can be used to generate the 20 Hz ring signal.
TIMR1
TIMR2
Address Interrupt status Interrupt mask Output pin Period
10H
DEXIR:T1EXP DEXIM:T1EXP No
(0..127)x 100 ms
4CH
DEXIR:TIN2 DEXIM:TIN2 TOUT2 (1..63) ms
Cyclic
yes (CNT=7)
yes(TMD=1)
There are two interrupt inputpins : XINTIN0, XINTIN1. Whenever signal level changes (eith rising or falling), a maskable
interrupt is generated which in turn will make an interrupt request on PCI bus if it is unmasked. The interrupt status bits are
ISTA:XINT0, ISTA:XINT1. The mask bits are IMASK:XINT0, IMASK:XINT1. In addition, the signal level can be read at bits
SQR:XIND0, SQR;XIND1. These pins can be used for monitor of SLIC hook state and/or DTMF data valid status.
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Publication Release Date: Sep 30, 1999
Revision 0.9