W6692 Datasheet, PDF (82/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
RA17-10 Address Bits
Used in transparent mode only. These bits are used for the first byte address comparisons.
8.2.11 B1_ch Address Register 2 B1_ADR2 Read/Write
Address A8H/2AH
Value after reset: 00H
7
6
5
4
3
2
1
0
RA27 RA26 RA25 RA24 RA23 RA22 RA21 RA20
RA27-20 Address Bits
Used in transparent mode only. These bits are used for the second byte address comparisons.
8.2.12 B1_ch Receive Frame Byte Count Low B1_RBCL Read Address ACH/2BH
Value after reset: 00H
7
6
5
4
3
2
1
0
RBC7 RBC6 RBC5 RBC4 RBC3 RBC2 RBC1 RBC0
RBC7-0 Receive Byte Count
Used in transparent mode only. Eight least significant bits of the total number of bytes are in a received frame. These bits are
valid only after a RME interrupt and remain valid until the frame is acknowledge via the RACK bit.
8.2.13 B1_ch Receive Frame Byte Count High B1_RBCH Read Address B0H/2CH
Value after reset: 00H
7
6
5
4
3
2
1
0
LOV RBC12 RBC11 RBC10 RBC9 RBC8
LOV Message Length Overflow
Used in transparent mode only. A "1" in this bit indicates a received message ≥ 8192 bytes. This bit is valid only after RME
interrupt and is cleared by the RACK command.
RBC12-8 Receive Byte Count
Used in transparent mode only. Five most significant bits of the total number of bytes are in a received frame. These bits are
valid only after a RME interrupt and remain valid until the frame is acknowledge via the RACK bit.
Note: The frame length equals RBC12-0. This length is between 1 and 8191. After a RME interrupt, the number of data
available in B1_RFIFO is frame length modulus threshold.
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Publication Release Date: Sep 30, 1999
Revision 0.9