W6692 Datasheet, PDF (92/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
1 = PCI clock is needed for PME# assertion. Default is 0.
Bits 18-16 Version
Default is 010b to indicate PCI Power Management Revision 1.1 compliant.
Bits 15-8 Next Item Pointer
Hardwired to 00_H , to indicate no further Capability list item.
Bits 7-0 Capability Identifier
Hardwired to 01_H , to indicate a PCI Power Management Identifier.
W6692 PCI ISDN S/T-Controller
8.4.11 Power Management Control/Status
Read/Write
Address 44_H
PCI Configuration Address: 44_H
Default: 0000_H for bits 31-16; X000,000X,0000,0000b for bits 15-0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Operational Data
PMCSR_BSE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Power Management Control/Status Register (PMCSR)
Bits 31-24 Operational Data Report Read
Reports the power operational data of whole PCI card. Not implemented. Read as 0.
Bits 23-16 PMCSR PCI to PCI Bridge Support Extensions Read
Not implemented. Read as 0.
Bits 15-0 are the Power Management Control/Status register. A sticky bit has an indeterminate value at time of initial operating
system boot. (It is not set/preset by PCI reset signal.)
Bit 15 PME_Status Read/Write-clear, Sticky
This bit is set when W6692 would normally assert the PME# signal independent of the state of the PME_En bit. Writig a "1"
to this bit will clear it and cause W6692 to stop asserting a PME# (if enabled). Writing a "0" has no effect.
PME event
occurred
No PME event
PME_En=0
PME_Status=1
PME# inactive
PME_Status=0
PME# inactive
PME-En=1
PME_Status=1
PME# active until PME-
Status is cleared
PME_Status=0
PME# inactive
Bits 14-13 Data_Scale Read
Used when interpreting the value of Data register. Not implemented. Read as 0.
Bits 12-9 Data_Select Read
Used to select which data is to be reported through the Data register and Data_Scale field. Not implemented. Read as 0.
Bit 8 PME_En Read/Write, Sticky
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Publication Release Date: Sep 30, 1999
Revision 0.9