W6692 Datasheet, PDF (59/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
This bit indicates the D_HDLC transmitter is busy. The XBZ bit is active from the transmission of opening flag to the
transmission of closing flag.
DRDY D Channel Ready
This bit indicates the status of layer 1 D channel.
0: The layer 1 D channel is not ready. No transmission is allowed.
1: The layer 1 D channel is ready. Layer 2 can transmit data to layer 1.
8.1.11 D_ch Receive Status Register
D_RSTA Read
Address 28H/0AH
Value after reset: 20H
7
6
5
4
3
2
1
0
RDOV CRCE RMB
RDOV Receive Data Overflow
A "1" indicates that the D_RFIFO is overflow. The incoming data will overwrite data in the receive FIFO. The data overflow
condition will set both the status and interrupt bits. It is recommended that software must read the RDOV bit after reading data
from D_RFIFO at RMR or RME interrupt. The software must abort the data and issue a RRST command to reset the receiver if
RDOV = 1. The frame overflow condition will not set this bit.
CRCE CRC Error
This bit indicates the result of frame CRC check:
0: CRC correct
1: CRC error
RMB Receive Message Aborted
A "1" means that a sequence of seven 1's was received and the frame is aborted. Software must issue RRST command to reset
the receiver.
Note: Normally D_RSTA register should be read by the microprocessor after a D_RME interrupt. The contents of D_RSTA are
valid only after a D_RME interrupt and remain valid until the frame is acknowledged via a RACK bit.
8.1.12 D_ch SAPI Address Mask D_SAM Read/Write Address 2CH/0BH
Value after reset: 00H
7
6
5
4
3
2
1
0
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Publication Release Date: Sep 30, 1999
Revision 0.9