W6692 Datasheet, PDF (62/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
8.1.19 D_ch Receive Frame Byte Count Low
D_RBCL
W6692 PCI ISDN S/T-Controller
Read
Address 48H/12H
Value after reset: 00H
7
6
5
4
3
2
1
0
RBC7 RBC6 RBC5 RBC4 RBC3 RBC2 RBC1 RBC0
RBC7-0 Receive Byte Count
Eight least significant bits of the total frame length. Bits RBC5-0 also indicate the length of the data currently available in
D_RFIFO. These bits are valid only after an D_RME interrupt and remain valid until the frame is acknowledged via the RACK
command.
8.1.20 Timer 2
TIMR2
Write Address 4CH/13H
Value after reset : 00H
7
6
5
4
3
2
1
0
TMD TIDLE TCN5 TCN4 TCN3 TCN2 TCN1 TCN0
TMD Timer 2 Mode
0: One shot count down mode. The timer starts when it is written a non-zero count value and stops when it reaches zero.
1: Cyclic timer mode. The timer starts when it is written a non-zero count value and counts cyclically (periodically) with the
count value.
In both cases, a maskable interrupt TIN2 is generated every time the timer reaches zero. When timer starts, pin TOUT2
changes to HIGH and toggles every half count time. Therefore, the period of TOUT2 equals count value.
In both cases, timer counts with the new value if it is written again before expiration.
The timer is stopped when it expires (TMD=0), or by writting zero count value (TMD=0 or 1).
TIDLE TOUT2 Idle
This bit defines value of TOUT2 pin when timer if off.
TCN5-0 Timer 2 Count Value
0: Timer is off.
1-63: Timer count value in unit of ms.
8.1.21 Layer 1_Ready Code
Value after reset: 0CH
7
6
5
4
L1_RC
Read/Write
3
2
1
0
RC3 RC2 RC1 RC0
Address 50H/14H
-62 -
Publication Release Date: Sep 30, 1999
Revision 0.9