W6692 Datasheet, PDF (15/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
PME
60
TOUT2
XINTIN0
XINTIN1
IO0-IO10
XAD7-XAD0
XALE
XRDB
XWRB
20
52
53
79,78,77,29,28,
27,26,4,3,2,1
29,28,27,26,
4,3,2,1
77
78
79
VDDD
VDDA
VDDB
VSSD
VSSA
VSSB
17,58,67,83
51
6,32,43,89
16,59,68,82
48
5,31,42,88
W6692 PCI ISDN S/T-Controller
O
Power Management Event Signal. Level triggered, active HIGH. Drive
a transistor to PME# in PCI slot.
Peripheral Control
O
Timer 2 output. A square wave with 50 % duty cycle, 1~63 ms period
can be generated.
I
A level change (either direction) will generate a maskable interrupt on
the PCI bus interrupt request pin INTA#.
I
A level change (either direction) will generate a maskable interrupt on
the PCI bus interrupt request pin INTA#.
I/O
When confiured as simple IO mode (PCTL:XMODE = 0), these pins
can read/write data from/to peripheral components. The pin directions
are selected via register.
I/O
When configured as microprocessor mode (PCTL:XMODE = 1),
address and data are multiplexed on these pins.
O
When configured as microprocessor mode (PCTL:XMODE = 1), this is
the Address Latch Enable output.
O
When configured as microprocessor mode (PCTL:XMODE = 1), this is
the read pulse.
O
When configured as microprocessor mode (PCTL:XMODE = 1), this is
the write pulse.
Power and Ground
I
Digital Power Supply (5V±5%).
I
Analog Power Supply (5V±5%).
I
PCI Bus Power Supply.
I
Digital Ground.
I
Analog Ground.
I
PCI Bus Ground.
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Publication Release Date: Sep 30, 1999
Revision 0.9