W6692 Datasheet, PDF (79/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
1
1
Layer 1 → PCM, PCM → HDLC
Note: The connection with micro-controller is through HDLC controller. When HDLC connects with layer 1, either transparent
or extended transparent mode can be used. When HDLC connects with PCM port, only extended transparent mode can be used
and the EPCM bit must be set to enable PCM function.
SW56 Switch 56 Traffic
0: The data rate in B1 channel is 64 kbps.
1: The data rate in B1 channel is 56 kbps. The most significant bit in each octet is fixed at "1".
Note: In 56 kbps mode, only transparent mode can be used.
FTS1-0 FIFO Threshold Select
These two bits determine the B1 channel receive and transmit FIFO's threshold setting. An interrupt is generated when the
number of received data or the number of vacancies in XFIFO reaches the threshold value.
FTS1
0
0
1
1
FTS0
0
1
0
1
Threshold (byte)
64
Reserved
96
Not allowed
8.2.5 B1_ch Extended Interrupt Register B1_EXIR Read_clear Address 90H/24H
Value after reset: 00H
7
6
5
4
3
RMR RME RDOV
2
1
0
XFR XDUN
RMR Receive Message Ready
At least a threshold lenth of data has been stored in the B1_RFIFO.
RME Receive Message End
Used in transparent mode only. The last block of a frame has been received. The frame length can be found in B1_RBCH +
B1_RBCL registers. The number of data available in the B1_RFIFO equals frame lenth modulus threshold. The result of CRC
check is indicated by B1_STAR:CRCE bit.
When the number of last block of a frame equals the threshold, only RME interrupt is generated.
RDOV Receive Data Overflow
Data overflow occurs in the receive FIFO. The incoming data will overwrite the data in the receive FIFO.
XFR Transmit FIFO Ready
This interrupt indicates that up to a threshold length of data can be written into the B1_XFIFO.
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Publication Release Date: Sep 30, 1999
Revision 0.9