W6692 Datasheet, PDF (3/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
TABLE OF CONTENTS
W6692 PCI ISDN S/T-Controller
1. GENERAL DESCRIPTION..........................................................................................................9
2. FEATURES ...................................................................................................................................9
3. PIN CONFIGURATION ............................................................................................................10
4. PIN DESCRIPTION ...................................................................................................................13
5. SYSTEM DIAGRAM AND APPLICATIONS...........................................................................16
6. BLOCK DIAGRAM....................................................................................................................17
7. FUNCTIONAL DESCRIPTIONS...............................................................................................18
7.1 Main Block Functions......................................................................................................................................................18
7.2 Layer 1 Functions Descriptions.......................................................................................................................................19
7.2.1 S/T Interface Transmitter/Receiver .............................................................................................................................19
7.2.2 Receiver Clock Recovery And Timing Generation ......................................................................................................24
7.2.3 Layer 1 Activation/Deactivation..................................................................................................................................24
7.2.3.1 States Descriptions And Command/Indication Codes ...........................................................................................24
7.2.3.2 State Transition Diagrams....................................................................................................................................26
7.2.4 D Channel Access Control ..........................................................................................................................................30
7.2.5 Frame Alignment........................................................................................................................................................30
7.2.5.1 FAinfA_1fr ..........................................................................................................................................................31
7.2.5.2 FAinfB_1fr ..........................................................................................................................................................31
7.2.5.3 FAinfD_1fr ..........................................................................................................................................................32
7.2.5.4 FAinfA_kfr ..........................................................................................................................................................32
7.2.5.5 FAinfB_kfr ..........................................................................................................................................................33
7.2.5.6 FAinfD_kfr ..........................................................................................................................................................33
7.2.5.7 Faregain...............................................................................................................................................................34
7.2.6 Multiframe Synchronization .......................................................................................................................................34
7.2.7 Test Functions ............................................................................................................................................................36
7.3 Serial Interface Bus .........................................................................................................................................................38
7.4 B Channel Switching .......................................................................................................................................................38
7.5 PCM Port.........................................................................................................................................................................40
7.6 D Channel HDLC Controller ..........................................................................................................................................40
7.6.1 D Channel Message Transfer Modes...........................................................................................................................41
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Publication Release Date: Sep 30, 1999
Revision 0.9