W6692 Datasheet, PDF (72/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
8.1.37 Monitor Transmit Channel 1
Value after reset: FFH
7
6
5
4
3
MO1X
W6692 PCI ISDN S/T-Controller
Read/Write
Address 71H/41H
2
1
0
Contains the Monitor channel data transmitted in GCI Monitor channel 1 according to the Monitor channel protocol.
8.1.38 Monitor Channel 1 Interrupt Register MO1I Read_clear
Value after reset: 00H
7
6
5
4
3
2
1
0
MDR1 MER1 MDA1 MAB1
MDR1
MER1
MDA1
MAB1
Monitor channel 1 Data Receive
Monitor channel 1 End of Reception
Monitor channel 1 Data Acknowledged
The remote end has acknowledged the Monitor byte being transmitted.
Monitor channel 1 Data Abort
Address 75H/42H
8.1.39 Monitor Channel 1 Control Register
MO1C
Read/Write Address 79H/43H
Value after reset: 00H
7
6
5
4
3
2
1
0
MRIE1 MRC1 MXIE1 MXC1
MRIE1 Monitor Channel 1 Receive Interrupt Enable
Monitor channel interrupt status MDR1, MER1 generation is enabled (1) or masked (0).
MRC1
interrupt
MR Bit Control
Determines the value of the MR bit:
0: MR bit always 1. In addition, the MDR1 interrupt is blocked, except for the first byte of a packet (if MRE=1).
1: MR internally controlled by the W6692 according to Monitor channel protocol. In addition, the MDR1
is enabled for all received bytes according to the Monitor channel protocol (if MRE=1).
MXIE1 Monitor channel 1 Transmit Interrupt Enable
Monitor interrupt status MDA1, MAB1 generation is enabled (1) or masked (0).
MXC1 MX bit Control
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Publication Release Date: Sep 30, 1999
Revision 0.9