W6692 Datasheet, PDF (54/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
The D_XFIFO has a length of 128 bytes.
W6692 PCI ISDN S/T-Controller
After an D_XFR interrupt, up to 64 bytes of data can be written into this FIFO for transmission. At the first time, up to 128
bytes of data can be written.
8.1.3 D_ch command register D_CMDR Read/Write Address 08H/02H
Value after reset: 00H
7
6
5
4
3
2
1
0
RACK RRST
STT1 XMS
XME XRST
RACK Receive Acknowledge
After a D_RMR or D_RME interrupt, the processor must read out the data in D_RFIFO and then sets this bit to acknowledge
the interrupt.
RRST Receiver Reset
Setting this bit resets the D_ch HDLC receiver and clears the D_RFIFO data.
STT1 Start Timer 1
The timer 1 is started when this bit is set to one. The timer is stopped when it expires or by a write of the TIMR1 register.
XMS Transmit Message Start/Continue
Setting this bit will start or continue the transmission of a frame. The opening flag is automatically added by the HDLC
controller.
XME Transmit Message End
Setting this bit indicates the end of frame transmission.. The D_ch HDLC controller automatically appends the CRC and the
closing flag after the data transmission.
Note: If the frame ≤ 64 bytes, XME plus XMS commands must be issued at the same time.
XRST Transmitter Reset
Setting this bit resets the D_ch HDLC transmitter and clears the D_XFIFO. The transmitter will send inter frame time fill
pattern (which is 1's) immediately. This command also results in a transmit FIFO ready condition.
A read of this register returns the last written value.
8.1.4 D_ch Mode Register D_MODE Read/Write Address 0CH/03H
Value after reset : 00H
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Publication Release Date: Sep 30, 1999
Revision 0.9