W6692 Datasheet, PDF (86/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
Bits 31-16 are Status register and bits 15-0 are Command register. Reads to Status register behave normally. Bits in Status
register are cleared if the corresponding write data bits are '1' in a write operation.
Bits 15-0 are Command register. When 00_H is written to this register, the device is logically disconnected from the PCI bus for
all accesses except configuration accesses. The power up value of Command register is 00 _H
.
Bit 31 DPE Detected Parity Error R/W_clr
1 = A parity error is detected.
0 = No parity error is detected.
Bit 30 SSE Signaled System Error
Not implemented. Read as 0.
Bits 29-28 Master Aborted, Target Aborted
Not implemented. Read as 0.
Bit 27 STA Signaled Target Abort
1 = Target Abort is signaled.
0 = Target Abort is not signaled.
R/W_clr
Bits 26-25 DEVSEL Timing Read_only
01 = Medium DEVSEL# timing.
Bits 24 PERR# Asserted
Not implemented. Read as 0.
Bit 23 FBT Fast Back-to-back Transaction Read_only
0 = Unable to accept fast back-to-back transaction.
Bit 22 UDF User Definable Features Read_only
0 = Unable to support User Definable Features.
Bit 21 66M 66 MHz Function Read_only
0 = Support 33 MHz only.
Bit 20 CAP Capability Read_only
1 = Power management capability is supported.
Bits 19-16 Reserved Read as 0
Bits 15-10 Reserved Read as 0
Bits 9 Fast Back-to-back
Not implemented. Read as 0.
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Publication Release Date: Sep 30, 1999
Revision 0.9