W6692 Datasheet, PDF (41/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

S frame
U frame
0 0 0 0SS 0 1
M M M P/F M M 1 1
Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
N(R)
P/F
7.6.1 D Channel Message Transfer Modes
The D channel HDLC controller operates in transparent mode.
Chracteristics:
- Receive frame address recognition
- Address comparison maskable bit-by-bit
- Flag generation / deletion
- Zero bit insertion/ deletion
- Frame Check Sequence (FCS) generation/ check with CRC_ITU-T
Note. The LAPD protocol uses the CRC_ITU-T for Frame Check Sequence. The polynominal is X¹⁶ + X¹² + X⁵ + 1.
For address recognition, the W6692 provides four programmable registers for individual SAPI and TEI values, SAP1-2 and
TEI1-2, plus two fixed values for group SAPI and TEI, SAPG and TEIG. The SAPG equals FEH or FCH which corresponds to
SAPI = 63 for layer management procedure. The TEIG equals FFH which corresponds to TEI = 127 for automatic TEI
assignment procedure. The address combinations are :
- SAP1 + TEI1
- SAP1 + FFH
- SAP2 + TEI2
- SAP2 + FFH
- FEH (FCH) + TEI1
- FEH (FCH) + TEI2
- FEH (FCH) + FFH
The receive frame address comparisons can be disabled (masked) per bit basis with the D_SAM and D_TAM registers, but
comparisons with the SAPG or TEIG cannot be disabled.
7.6.2 Reception of Frames in D Channel
A 128-byte FIFO is provided in the receive direction. The data movement between receive FIFO and micro-processor is
handled by interrupts.
There are two interrupt sources: Receive Message Ready (D_RMR) and Receive Message End (D_RME). The D_RMR
interrupt indicates that at least 64 bytes of data have been received and the message/ frame is not ended. Upon D_RMR interrupt,
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Publication Release Date: Sep 30, 1999
Revision 0.9