W6692 Datasheet, PDF (68/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
Monitor channel interrupt status MDR0, MER0 generation is enabled (1) or masked (0).
MRC0
interrupt
MR Bit Control
Determines the value of the MR bit:
0: MR bit always 1. In addition, the MDR0 interrupt is blocked, except for the first byte of a packet (if MRE=1).
1: MR internally controlled by the W6692 according to Monitor channel protocol. In addition, the MDR0
is enabled for all received bytes according to the Monitor channel protocol (if MRE=1).
MXIE0 Monitor channel 0 Transmit Interrupt Enable
Monitor interrupt status MDA0, MAB0 generation is enabled (1) or masked (0).
MXC0
MX bit Control
Determines the value of the MX bit:
0: MX always 1.
1: MX internally controlled by the W6692 according to Monitor channel protocol.
8.1.32 GCI Mode Control/Status Register
7CH/1FH
GCR
Read/Write
Value after reset: 00H
7
6
5
MAC0 MAC1
4
3
2
TLP GRLP SPU
1
0
PD GMODE
Address
MAC0
to 1.
MOX) in
Monitor Transmit Channel 0 Active (Read Only)
Data transmission is in progress in GCI mode Monitor channel 0.
0: the previous transmission has been terminated. Before starting a transmission, the microprocessor should verify
that the transmitter is inactive.
1: after having written data into the Monitor Transmit Channel 0 (MO0X) register, the microprocessor sets this bit
This enables the MX bit to go active (0), indicating the presence of valid Monitor channel data (contents of
the correspond frame.
MAC1
to 1.
MOX) in
Monitor Transmit Channel 1 Active (Read Only)
Data transmission is in progress in GCI mode Monitor channel 1.
0: the previous transmission has been terminated. Before starting a transmission, the microprocessor should verify
that the transmitter is inactive.
1: after having written data into the Monitor Transmit Channel 1 (MO1X) register, the microprocessor sets this bit
This enables the MX bit to go active (0), indicating the presence of valid Monitor channel data (contents of
the correspond frame.
TLP Test Loop
When set this bit to 1 both the DOUT and DIN lines are internally connected together. The GCI mode loop-back test
function: DOUT is internally connected with DIN, external input on DIN is ignored.
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Publication Release Date: Sep 30, 1999
Revision 0.9