W6692 Datasheet, PDF (65/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
XIND1 XINTIN1 Data
This bit reflects the current level of XINTIN1 pin.
W6692 PCI ISDN S/T-Controller
XIND0 XINTIN0 Data
This bit reflects the current level of XINTIN0 pin.
MSYN Multiframe Synchronization
When this bit is "1", a multiframe synchronization is achived, i.e the S/T receiver has synchronized to the received F_A and M
bit patterns.
SCIE S Channel Change Interrupt Enable
This bit reflects the bit written in the SQX register.
S1-4 Received S Bits
These are the S bits received in NT to TE direction in frames 1, 6, 11 and 16. S1 is in frame 1, S2 is in frame 6 etc. This four
bits are double buffered.
8.1.26 S/Q Channel Transmit Register SQX
Read/Write
Address 64H/19H
Value after reset: 0FH
7
6
5
4
3
2
1
0
SCIE
Q1
Q2
Q3
Q4
SCIE S Channel Change Interrupt Enable
This bit is used to enable/disable the generation of CIR:SCC status bit and interrupt.
0 : Status bit and interrupt are disabled.
1 : Status bit and interrupt are enabled.
Q1-4 Transmitted Q Bits
These are the transmitted Q channels in F_A bit positions in frames 1, 6, 11 and 16. Q1 is in frame 1 and Q2 is in frame 6 etc.
A read to this register returns the previous written value.
8.1.27 Peripheral Control Register
PCTL
Read/Write
Address 68H/1AH
Value after reset: 00H
7
6
5
4
3
2
1
0
OE5 OE4 OE3 OE2 OE1 OE0 XMODE PXC
OE5 Direction Control for IO10
Used when XMODE=0 only.
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Publication Release Date: Sep 30, 1999
Revision 0.9