W6692 Datasheet, PDF (63/104 Pages) Winbond – PCI Bus ISDN S/T-Controller

Preliminary Data Sheet
W6692 PCI ISDN S/T-Controller
RC3-0 Ready Code
When GCI bus is being enabled, these four programmable bits are allowed to program different Layer 1_Ready Code (AI:
Activation Indication) by user. For example: Siemens PEB2091: AI=1100, Motorola MC145572: AI=1100.
8.1.22 Control Register
Value after reset : 00H
7
6
5
0
0
SRST
CTL Read/Write Address 54H/15H
4
3
2
1
0
0
OPS1 OPS0
SRST Software Reset
When this bit is set to "1", a software reset signal is activated. The effects of this reset signal are equivalent to the hardware
reset pin , except that it does not reset the PCI interface circuit.
This bit is not auto-clear, the software must write "0" to this bit to exit from the reset mode.
Note: When SRST = 1, the chip is in reset state. Read or write to any of the registers is inhibited at this time. The SRST bit is
write-only.
OPS1-0 Output Phase Delay Compensation Select1-0
These two bits select the output phase delay compensation.
OPS1 OPS0 Effect
0
0 No output phase delay compensation
0
1 Output phase delay compensation 260ns
1
0 Output phase delay compensation 520 ns
1
1 Output phase delay compensation 1040 ns
8.1.23 Command/Indication Receive Register CIR Read
Address 58H/16H
Value after reset: 0FH
7
6
5
SCC ICC
4
3
2
1
0
CODR3 CODR2 CODR1 CODR0
SCC S Channel Change
A change in the received 4-bit S channel has been detected. The new code can be read from the SQR register. This bit is
cleared via a read of the SQR register.
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Publication Release Date: Sep 30, 1999
Revision 0.9