SPRUGZ8D Datasheet, PDF (955/3016 Pages) Texas Instruments – Technical Reference Manual

www.ti.com
CONTROL_MODULE Registers
3.2.100 DSP_INTMUX_63_66 Register (offset = F30h) [reset = 0h]
DSP_INTMUX_63_66 is shown in Figure 3-101 and described in Table 3-103.
This register controls interrupt mux assignment for Interrupt 63 to 66
Figure 3-101. DSP_INTMUX_63_66 Register
31
30
29
28
27
26
25
24
Rsvd4
INT_MUX_66
0h
R/W-0h
23
22
21
20
19
18
17
16
Rsvd3
INT_MUX_65
0h
R/W-0h
15
14
13
12
11
10
9
8
Rsvd2
INT_MUX_64
0h
R/W-0h
7
6
5
4
3
2
1
0
Rsvd
INT_MUX_63
0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Bit
31-30
29-24
23-22
21-16
15-14
13-8
7-6
5-0
Field
Rsvd4
INT_MUX_66
Rsvd3
INT_MUX_65
Rsvd2
INT_MUX_64
Rsvd
INT_MUX_63
Table 3-103. DSP_INTMUX_63_66 Register Field Descriptions
Type
R/W
R/W
R/W
R/W
Reset
0h
0h
0h
0h
0h
0h
0h
0h
Description
Reserved-Read returns 0
Interrupt mux for GEM s interrupt number 66
Reserved-Read returns 0
Interrupt mux for GEM s interrupt number 65
Reserved-Read returns 0
Interrupt mux for GEM s interrupt number 64
Reserved
Interrupt mux for GEM s interrupt number 63
SPRUGZ8D – 14 November 2011 – Revised April 2013
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Control Module 955