SPRUGZ8D Datasheet, PDF (1975/3016 Pages) Texas Instruments – Technical Reference Manual

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Name
I2C_SCL
I2C_SDA
Architecture
Table 15-1. Signal Pads
Default Operating
Mode
In/ Out
In/ Out
I2C Mode
Description
I2C serial CLK line
Open-drain output buffer. Requires external pull-up resistor (Rp).
I2C serial data line
Open-drain output buffer. Requires external pull-up resistor (Rp).
15.2.2 I2C Reset
The I2C module can be reset in the following three ways:
• A device reset causes all registers to be reset to their default values.
• A software reset by setting the SRST bit in the I2C_SYSC register. This bit has exactly the same
action on the module logic as the device reset. All registers are reset to power up reset values.
• The I2C_EN bit in the I2C_CON register can be used to hold the I2C module in reset. When the device
reset is removed, I2C_EN = 0 keeps the functional part of I2C module in reset state and all
configuration registers can be accessed. I2C_EN = 0 does not reset the registers to power up reset
values.
Table 15-2. Reset State of I2C Signals
Pin
I/O/Z ⁽¹⁾
SDA
I/O/Z
SCL
I/O/Z
(1) _{I = Input, O = Outpu, Z = High impedance}
System Reset
High impedance
High impedance
I2C Reset
(I2C_EN = 0)
High impedance
High impedance
15.2.3 Data Validity
The data on the SDA line must be stable during the high period of the clock. The high and low states of
the data line can only change when the clock signal on the SCL line is LOW.
I2Cx_SDA
Figure 15-3. Bit Transfer on the I2C Bus
Data line
stable data
I2Cx_SCL
Change of data
allowed
SPRUGZ8D – 14 November 2011 – Revised April 2013
Inter-Integrated Circuit (I2C) Controller Module
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