SPRUGZ8D Datasheet, PDF (734/3016 Pages) Texas Instruments – Technical Reference Manual

PRCM Registers
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2.10.11.1 CM_SGX_CLKSTCTRL Register (offset = 0h) [reset = 1h]
CM_SGX_CLKSTCTRL is shown in Figure 2-221 and described in Table 2-247.
This register enables the domain power state transition. It controls the SW supervised clock domain state
transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the
domain.
Figure 2-221. CM_SGX_CLKSTCTRL Register
31
30
29
28
27
26
Reserved
R-0h
23
22
21
20
19
18
Reserved
R-0h
15
14
13
12
11
10
Reserved
R-0h
7
6
5
4
3
2
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
25
24
Reserved
R-0h
17
16
9
8
CLKACTIVITY_SGX_
GCLK
R-0h
1
0
CLKTRCTRL
R/W-1h
Bit
31-26
25-9
8
7-2
1-0
Table 2-247. CM_SGX_CLKSTCTRL Register Field Descriptions
Field
Type
Reserved
R
Reserved
R
CLKACTIVITY_SGX_GCL R
K
Reserved
R
CLKTRCTRL
R/W
Reset
0h
0h
0h
0h
1h
Description
This field indicates the state of the SGX_GCLK clock in the domain.
0x0: Inact: Corresponding clock is gated
0x1: Act: Corresponding clock is active
Controls the clock state transition of the SGX clock domain in SGX
power domain.
0x0: NO_SLEEP: Sleep transition cannot be initiated. Wakeup
transition may however occur.
0x1: SW_SLEEP: Start a software forced sleep transition on the
domain.
0x2: SW_WKUP: Start a software forced wake-up transition on the
domain.
0x3: HW_AUTO: Automatic transition is enabled. Sleep and wakeup
transition are based upon hardware conditions.
734 Power, Reset, and Clock Management (PRCM) Module
SPRUGZ8D – 14 November 2011 – Revised April 2013
Copyright © 2011–2013, Texas Instruments Incorporated
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