SPRUGZ8D Datasheet, PDF (2399/3016 Pages) Texas Instruments – Technical Reference Manual

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PCIESS Memory Map
19.5.1.41 OB_OFFSETn_HI Register (0x200 + N*8 + 0x4)
The outbound translation region N offset high register (OB_OFFSETn_HI ) is described in the figure and
table below.
Figure 19-45. OB_OFFSETn_HI Register
31
0
OB_OFFSETn_HI
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
31-0
Field
OB_OFFSETn_HI
Table 19-51. OB_OFFSETn_HI Register Field Descriptions
Value
0-FFFF FFFFh
Description
Offset bits 31-0 for translation region N (N=0-31)
19.5.1.42 IB_BAR0 Register
The inbound translation bar match 0 register (IB_BAR0 ) is described in the figure and table below.
Figure 19-46. IB_BAR0 Register
31
Reserved
R-0
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
16
3
2
0
IB_BAR0
R/W-0
Bit
31-3
2-0
Field
Reserved
IB_BAR0
Table 19-52. IB_BAR0 Register Field Descriptions
Value
0
0-7h
Description
Reserved
BAR number to match for inbound translation region 0
19.5.1.43 IB_START0_LO Register
The inbound translation 0 start address low register (IB_START0_LO) is described in the figure and table
below.
Figure 19-47. IB_START0_LO Register
31
8
IB_START0_LO
R/W-0
7
0
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
31-8
7-0
Field
IB_START0_LO
Reserved
Table 19-53. IB_START0_LO Register Field Descriptions
Value
0-FF FFFFh
0
Description
Start address bits 31-8 for inbound translation region 0.
Reserved
SPRUGZ8D – 14 November 2011 – Revised April 2013
Peripheral Component Interconnect Express (PCIe) Module
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