SPRUGZ8D Datasheet, PDF (1811/3016 Pages) Texas Instruments – Technical Reference Manual

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HDMI Registers
13.3.1.9 Configuration of Clocks Register (HDMI_WP_CLK)
The configuration of clocks register is shown in Figure 13-18 and described in Table 13-26.
Figure 13-18. Configuration of Clocks Register (HDMI_WP_CLK)
31
17
Reserved
R-0h
15
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
6
5
CEC_DIV
R/W-0h
16
OCP_TIME_
OUT_DIS
R/W-0h
0
Table 13-26. Configuration of Clocks Register (HDMI_WP_CLK) Field Descriptions
Bit
31-17
16
Field
Reserved
OCP_TIME_OUT_DIS
15-6
5-0
Reserved
CEC_DIV
Value
0
0
1
0
0
1
Description
Reserved
Timeout in case CEC_DDC_CLK not provided.
Timeout after 4095 OCP clock cycles after inactivity. HDMI Core register interface
(due to CEC_DDC_CLK not provided to HDMI). An interrupt is generated. No error
response is provided on the OCP interface.
No timeout capability
Reserved
Defines the divisor value to be used for the generation of the CEC clock (1 MHz)
from the input CEC_DDC clock (48 MHz). If 48 MHz is provided, the division by 24 is
required (18h) to get the expected CEC clock speed (2 MHz) The valid values are
from 0 to 63.
Gated
Free-running
SPRUGZ8D – 14 November 2011 – Revised April 2013
High-Definition Multimedia Interface (HDMI)
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