SPRUGZ8D Datasheet, PDF (718/3016 Pages) Texas Instruments – Technical Reference Manual

PRCM Registers
2.10.7.5 CM_DEFAULT_SATA_CLKCTRL Register (offset = 60h) [reset = 70000h]
CM_DEFAULT_SATA_CLKCTRL is shown in Figure 2-209 and described in Table 2-231.
This register manages the SATA clocks.
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Figure 2-209. CM_DEFAULT_SATA_CLKCTRL Register
31
30
29
28
27
26
25
24
Reserved
R-0h
23
22
21
20
19
18
17
16
Reserved
STBYST
IDLEST
R-0h
R-1h
R-3h
15
14
13
12
11
10
9
8
Reserved
R-0h
7
6
5
4
3
2
1
0
Reserved
MODULEMODE
R-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Bit
31-19
18
17-16
15-2
1-0
Table 2-231. CM_DEFAULT_SATA_CLKCTRL Register Field Descriptions
Field
Reserved
STBYST
IDLEST
Reserved
MODULEMODE
Type
R
R
R
R
R/W
Reset
0h
1h
3h
0h
0h
Description
Module standby status.
0x0: Func: Module is functional (not in standby)
0x1: Standby: Module is in standby
Module idle status.
0x0: Func: Module is fully functional, including INTERCONN
0x1: Trans: Module is performing transition: wakeup, or sleep, or
sleep abortion
0x2: Idle: Module is in Idle mode (only INTERCONN part). It is
functional if using separate functional clock
0x3: Disable: Module is disabled and cannot be accessed
Control the way mandatory clocks are managed.
0x0: DISABLED: Module is disable by SW. Any INTERCONN access
to module results in an error, except if resulting from a module
wakeup (asynchronous wakeup).
0x1: RESERVED
0x2: ENABLE: Module is explicitly enabled. Interface clock (if not
used for functions) may be gated according to the clock domain
state. Functional clocks are guarantied to stay present. As long as in
this configuration, power domain sleep transition cannot happen.
0x3: RESERVED
718 Power, Reset, and Clock Management (PRCM) Module
SPRUGZ8D – 14 November 2011 – Revised April 2013
Copyright © 2011–2013, Texas Instruments Incorporated
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