SPRUGZ8D Datasheet, PDF (1584/3016 Pages) Texas Instruments – Technical Reference Manual

Registers
9.4.3.2 Subsystem Software Reset Register (SOFT_RESET) (0x904)
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Figure 9-151. Subsystem Software Reset Register (SOFT_RESET)
31
Reserved
R-0
15
1
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
16
0
SOFT_RESET
R/W-0
Table 9-157. Subsystem Software Reset Register (SOFT_RESET) Field Descriptions
Bit
31-1
0
Field
Reserved
SOFT_RESET
Value
0
0-1
Description
Read as zero.
Software reset - Writing a one to this bit causes the CPGMACSS_R logic to be reset (INT, REGS,
CPPI). Software reset occurs on the clock following the register bit write.
9.4.3.3 Subsystem Control Register (CONTROL) (0x908)
Figure 9-152. Subsystem Control Register (CONTROL)
31
Reserved
R-0
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
4
3
2
MMR_STDBYMODE
R/W-2h
16
1
0
MMR_IDLEMODE
R/W-2h
Table 9-158. Subsystem Control Register (CONTROL) Field Descriptions
Bit
31-4
3-2
Field
Reserved
MMR_STDBYMODE
1-0 MMR_IDLEMODE
Value
0
0-3h
0-3h
Description
Read as zero.
Standbymode MMR bits. This field is used to cause the CPSW_3GSS_R to go to standby mode
(software standby). Smart standby is not supported.
Idlemode MMR bits. This field is used to cause the CPSW_3GSS_R to go to idle mode
(software idle). Smart idle is not supported.
1584
3PSW Ethernet Subsystem (EMAC)
SPRUGZ8D – 14 November 2011 – Revised April 2013
Copyright © 2011–2013, Texas Instruments Incorporated
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