SPRUGZ8D Datasheet, PDF (2684/3016 Pages) Texas Instruments – Technical Reference Manual

Architecture
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24.2.3.2.1 Receive (RX)
When software flow control operation is enabled, the UART compares incoming data with XOFF1/2
programmed characters (in certain cases XOFF1 and XOFF2 must be received sequentially). When the
correct XOFF characters are received, transmission is halted after completing transmission of the current
character. XOFF detection also sets IIR[4] (if enabled via IER[5]) and causes the interrupt line to go low.
To resume transmission a XON1/2 character must be received (in certain cases XON1 and XON2 must be
received sequentially). When the correct XON characters are received IIR[4] is cleared and the XOFF
interrupt disappears.
NOTE: If a parity, framing or break error occurs while receiving a software flow control character,
this character will be treated as normal data and will be written to the RX FIFO.
When XON-any and special character detect are disabled and software flow control is enabled no valid
XON or XOFF characters are written to the RX FIFO. For example, EFR[1:0] = 10, if XON1 and XOFF1
characters are received they do not get written to the RX FIFO. In the case where pairs of software flow
characters are programmed to be received sequentially (EFR[1:0] = 11) the software flow characters are
not written to the RX FIFO if they are received sequentially. However, received XON1/XOFF1 characters
must be written to the RX FIFO if the subsequent character is not XON2/XOFF2.
24.2.3.2.2 Transmit (TX)
• XOFF1: Two characters are transmitted when the RX FIFO has passed the programmed trigger level
TCR[3:0].
• XON1: Two characters are transmitted when the RX FIFO reaches the trigger level programmed via
TCR[7:4].
NOTE: If after an XOFF character has been sent, software flow control is disabled, the module
transmits XON characters automatically to enable normal transmission to proceed.
The transmission of XOFF/XON (s) follows the exact same protocol as transmission of an ordinary byte
from the TX FIFO. This means that even if the word length is set to be 5, 6 or 7 characters then the 5, 6 or
7 least significant bits of XOFF1,2/XON1,2 are transmitted. Note that the transmission of 5, 6, or 7 bits of
a character is seldom done but this functionality is included to maintain compatibility with earlier designs. It
is assumed that software flow control and hardware flow control will never be enabled simultaneously.
24.2.3.3 Break and Time-Out Conditions
24.2.3.3.1 Time-Out Counter
An RX idle condition is detected when the receiver line, RX, has been high for a time equivalent to 4X
programmed word length+12 bits. The receiver line is sampled midway through each bit. For sleep mode
the counter is reset when there is activity on the RX line. For the timeout interrupt, the counter only counts
when there is data in the RX FIFO and the count is reset when there is activity on the RX line or when the
RHR is read.
24.2.3.3.2 Break Condition
When a break condition occurs, the TX line is pulled low. A break condition is activated by setting LCR[6].
Be aware that the break condition is not aligned on word stream; that is, a break condition can occur in
the middle of a character. The only way to send a break condition on a full character, is:
• Reset transmit FIFO (if enabled)
• Wait for transmit shift register becomes empty (LSR[6] = 1)
• Take a guard time according to stop bit definition
• Set LCR[6] to 1
2684 UART/IrDA/CIR Module
SPRUGZ8D – 14 November 2011 – Revised April 2013
Copyright © 2011–2013, Texas Instruments Incorporated
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