SPRUGZ8D Datasheet, PDF (49/3016 Pages) Texas Instruments – Technical Reference Manual

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9-81. CPDMA_INT RX Interrupt Mask Clear Register (RX_INTMASK_CLEAR) ..................................... 1536
9-82. CPDMA_INT DMA Interrupt Status (raw value) Register (DMA_INTSTAT_RAW) ............................ 1537
9-83. CPDMA_INT DMA Interrupt Status (masked value) Register (DMA_INTSTAT_MASKED) .................. 1537
9-84. CPDMA_INT DMA Interrupt Mask Set Register (DMA_INTMASK_SET) ....................................... 1538
9-85. CPDMA_INT DMA Interrupt Mask Clear Register (DMA_INTMASK_CLEAR) ................................ 1538
9-86. CPDMA_INT RX Channel Threshold Pending Channel Registers .............................................. 1539
9-87. CPDMA_INT RX Channel Free Buffer Count Registers .......................................................... 1539
9-88. CPDMA_STATERAM TX Channel Head Descriptor Pointers ................................................... 1539
9-89. CPDMA_STATERAM RX Channel Head Descriptor Pointers ................................................... 1540
9-90. CPDMA_STATERAM TX Channel Completion Pointer Registers .............................................. 1540
9-91. CPDMA_STATERAM RX Channel Completion Pointer Registers .............................................. 1540
9-92. Statistics Register ...................................................................................................... 1541
9-93. Statistics Register ...................................................................................................... 1545
9-94. Statistics Register ...................................................................................................... 1548
9-95. Identification and Version Register (CPTS_IDVER) ............................................................... 1550
9-96. Time Sync Control Register (CPTS_CONTROL) .................................................................. 1550
9-97. Reference Clock Select Register (CPTS_RFTCLK_SEL) ........................................................ 1551
9-98. Time Stamp Event Push Register (CPTS_TS_PUSH) ............................................................ 1551
9-99. Time Stamp Load Value Register (CPTS_TS_LOAD_VAL)...................................................... 1551
9-100. Time Stamp Load Enable Register (CPTS_TS_LOAD_EN)...................................................... 1552
9-101. Time Sync Interrupt Status Register Raw Register (CPTS_INTSTAT_RAW).................................. 1552
9-102. Time Sync Interrupt Status Register Masked Register (CPTS_INTSTAT_MASKED) ........................ 1552
9-103. Time Sync Interrupt Enable Register (CPTS_INT_ENABLE) .................................................... 1553
9-104. Event Interrupt Pop Register (CPTS_EVENT_POP) .............................................................. 1553
9-105. Event Low Register (CPTS_EVENT_LOW)......................................................................... 1553
9-106. Event High Register (CPTS_EVENT_HIGH) ....................................................................... 1554
9-107. Address Lookup Engine ID/Version Register (ALE_IDVER) ..................................................... 1554
9-108. ALE Control Register (ALE_CONTROL) ............................................................................ 1555
9-109. ALE Prescale Register (ALE_PRESCALE) ......................................................................... 1556
9-110. ALE Unknown VLAN Register (ALE_UNKNOWN_VLAN) ........................................................ 1557
9-111. ALE Table Control Register (ALE_TBLCTL)........................................................................ 1557
9-112. ALE Table Word 2 Register (ALE_TBLW2)......................................................................... 1558
9-113. ALE Table Word 1 Register (ALE_TBLW1)......................................................................... 1558
9-114. ALE Table Word 0 Register (ALE_TBLW0)......................................................................... 1558
9-115. ALE Port Control Registers ........................................................................................... 1559
9-116. CPGMAC_SL1 IDVER Register (SL1_IDVER)..................................................................... 1560
9-117. CPGMAC_SL1 MAC Control Register (SL1_MACCONTROL)................................................... 1560
9-118. CPGMAC_SL1 MAC Status Register (SL1_MACSTATUS) ...................................................... 1562
9-119. CPGMAC_SL1 Software Reset Register (SL1_SOFT_RESET) ................................................. 1563
9-120. CPGMAC_SL1 RX Maximum Length Register (SL1_RX_MAXLEN)............................................ 1563
9-121. CPGMAC_SL1 Backoff Random Number Generator Test Register (SL1_BOFFTEST)...................... 1564
9-122. CPGMAC_SL1 RX Pause Timer Register (SL1_RX_PAUSE) ................................................... 1564
9-123. CPGMAC_SL1 TX Pause Timer Register (SL1_TX_PAUSE).................................................... 1565
9-124. CPGMAC_SL1 Emulation Control Register (SL1_EMCONTROL)............................................... 1565
9-125. CPGMAC_SL1 RX Packet Priority to Header Priority Mapping Register (SL1_RX_Pri_Map) ............... 1566
9-126. CPGMAC_SL2 IDVER Register (SL2_IDVER)..................................................................... 1567
9-127. CPGMAC_SL2 MAC Control Register (SL2_MACCONTROL)................................................... 1567
9-128. CPGMAC_SL2 MAC Status Register (SL2_MACSTATUS) ...................................................... 1570
9-129. CPGMAC_SL2 Software Reset Register (SL2_SOFT_RESET) ................................................. 1570
SPRUGZ8D – 14 November 2011 – Revised April 2013
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List of Figures
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