SPRUGZ8D Datasheet, PDF (1277/3016 Pages) Texas Instruments – Technical Reference Manual

www.ti.com
DDR2/DDR3 Configuration Registers
7.8.3 DDR Related Control Module Registers
This section describes the EMIF PHY Clock Gate, VTP and DDR IO configuration registers which reside in
the device control module register map. Refer below register description for more details. See the device-
specific data manual for the base memory address of these registers.
Register Name
EMIF_CLK_GATE
DDR0_IO_CTRL
DDR1_IO_CTRL
DDR_VTP_CTRL_0
DDR_VTP_CTRL_1
Table 7-77. DDR Related Control Module Registers
Type
RW
RW
RW
RW
RW
Register Description
EMIF0/1 PHY Clock
gate Control Register
DDR Memory
Controller_0 IO Control
Register
DDR Memory
Controller_1 IO Control
Register
DDR VTP Control
Register
DDR VTP Control
Register
Register Reset
0xC
0x02131313
0x02131313
0x67
0x67
Address Offset
0x694
0xE04
0xE08
0xE0C
0xE10
7.8.3.1 EMIF0/1 Clock Gate Control Register
The EMIF0/1 Clock Gate Control Register ( EMIF_CLK_GATE) described in the figure and table below.
Figure 7-43. EMIF0/1 Clock Gate Control Register
31
Reserved
R-0
7
4
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
DDR1_CKE_
STATUS
R-1
2
DDR0_CKE_
STATUS
R-1
1
DDRPHY1_
CLK_GATE
R/W-0
8
0
DDRPHY0_
CLK_GATE
R/W-0
Bit
31-4
3
2
1
Field
Reserved
DDR1_CKE_
STATUS
DDR0_CKE_
STATUS
DDRPHY1_
CLK_GATE
0 DDRPHY0_
CLK_GATE
Table 7-78. EMIF0/1 Clock Gate Control Register Field Descriptions
Value
0
1
Description
Reserved
CKE status for DDR1
1 CKE status for DDR0
Enables/disables the clock to the DDR1 PHY .
0 DDR1 PHY clock enabled (running)
1 DDR1 PHY clock disabled (stopped)
Enables/disables the clock to the DDR0 PHY
0 DDR0 PHY clock enabled (running)
1 DDR0 PHY clock disabled (stopped)
SPRUGZ8D – 14 November 2011 – Revised April 2013
DDR2 and DDR3 Memory Controller
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
1277