SPRUGZ8D Datasheet, PDF (780/3016 Pages) Texas Instruments – Technical Reference Manual

PRCM Registers
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2.10.18.11 CM_ALWON_SYSCLK6_CLKSTCTRL Register (offset = 28h) [reset = 2h]
CM_ALWON_SYSCLK6_CLKSTCTRL is shown in Figure 2-256 and described in Table 2-289.
This register enables the domain power state transition. It controls the SW supervised clock domain state
transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the
domain.
Figure 2-256. CM_ALWON_SYSCLK6_CLKSTCTRL Register
31
30
29
28
27
26
25
24
Reserved
Reserved
R-0h
R-0h
23
22
21
20
19
18
17
16
Reserved
R-0h
15
14
13
12
11
10
Reserved
R-0h
9
8
CLKACTIVITY_SYSC
LK6_GCLK
R-0h
7
6
5
4
3
2
1
0
Reserved
CLKTRCTRL
R-0h
R-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Bit
31-26
25-9
8
7-2
1-0
Table 2-289. CM_ALWON_SYSCLK6_CLKSTCTRL Register Field Descriptions
Field
Reserved
Reserved
CLKACTIVITY_SYSCLK6
_GCLK
Type
R
R
R
Reserved
R
CLKTRCTRL
R
Reset
0h
0h
0h
0h
2h
Description
This field indicates the state of the SYSCLK6_GCLK clock in the
domain.
0x0: Inact: Corresponding clock is gated
0x1: Act: Corresponding clock is active
Controls the clock state transition of the SYSCLK6 clock domain in
Always ON power domain.
0x0: Reserved
0x1: Reserved
0x2: SW_WKUP: Start a software forced wake-up transition on the
domain.
0x3: Reserved
780 Power, Reset, and Clock Management (PRCM) Module
SPRUGZ8D – 14 November 2011 – Revised April 2013
Copyright © 2011–2013, Texas Instruments Incorporated
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