SPRUGZ8D Datasheet, PDF (1552/3016 Pages) Texas Instruments – Technical Reference Manual

Registers
9.4.1.80 Time Stamp Load Enable Register (CPTS_TS_LOAD_EN) (0x514)
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Figure 9-100. Time Stamp Load Enable Register (CPTS_TS_LOAD_EN)
31
1
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
0
TS_LOAD_EN
W-0
Table 9-104. Time Stamp Load Enable Register (CPTS_TS_LOAD_EN) Field Descriptions
Bit
31-1
0
Field
Reserved
TS_LOAD_EN
Value
0
0-1
Description
Reserved
Time Stamp Load. Writing a 1 to this bit enables the time stamp value to be written via the
CPTS_TS_LOAD_VAL register. This feature is included for test purposes. This bit is write only.
9.4.1.81 Time Sync Interrupt Status Register Raw Register (CPTS_INTSTAT_RAW) (0x520)
Figure 9-101. Time Sync Interrupt Status Register Raw Register (CPTS_INTSTAT_RAW)
31
1
0
Reserved
TS_PEND_RAW
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-105. Time Sync Interrupt Status Register Raw Register (CPTS_INTSTAT_RAW)
Field Descriptions
Bit
31-1
0
Field
Reserved
TS_PEND_RAW
Value
0
0-1
Description
Reserved
TS_PEND_RAW interrupt read (before enable). Writable when INT_TEST = 1. A 1 in this bit
indicates that there is one or more events in the event FIFO.
9.4.1.82 Time Sync Interrupt Status Register Masked Register (CPTS_INTSTAT_MASKED) (0x524)
Figure 9-102. Time Sync Interrupt Status Register Masked Register (CPTS_INTSTAT_MASKED)
31
1
0
Reserved
TS_PEND
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-106. Time Sync Interrupt Status Register Masked Register (CPTS_INTSTAT_MASKED)
Field Descriptions
Bit
31-1
0
Field
Reserved
TS_PEND
Value
0
0-1
Description
Reserved
TS_PEND masked interrupt read (after enable).
1552
3PSW Ethernet Subsystem (EMAC)
SPRUGZ8D – 14 November 2011 – Revised April 2013
Copyright © 2011–2013, Texas Instruments Incorporated
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