SPRUGZ8D Datasheet, PDF (1181/3016 Pages) Texas Instruments – Technical Reference Manual

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6.3.4 Address Management Using LISA Sections
In the device, there are either one ot two memory controllers (EMIFs).
Use Case
6.3.4.1 DMM Sections
The DMM section definition is certainly the very first step in the DMM software configuration, as it is about
defining the system address map to be used when accessing the SDRAM controllers.
A DMM section description fits in a single 32-bit register (DMM_LISA_MAP_x), where:
• SYS_ADDR defines the base address of the decoding range for the section
• SYS_SIZE defines the size of the section. Note that the encoding of this parameter is the number of
bits actually used in the upper 8-bits of the incoming system address.
• SDRC_ADDR defines the physical base address of the section in the external memory controller
• SDRC_ADDRSPC defines the address space used on the SDRAM controller when hitting this section.
The address space feature is not supported.
• SDRC_MAP defines the target memory controllers for this section. A section may hit a one or two
controllers. The section is not used if this parameter is set to zero.
• SDRC_INTL defines the granularity of the interleaving if the section is mapped on more than one
memory controllers
A couple of examples are given in the next subsections.
SPRUGZ8D – 14 November 2011 – Revised April 2013
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