SPRUGZ8D Datasheet, PDF (655/3016 Pages) Texas Instruments – Technical Reference Manual

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2.10.1.129 DDRPLL_TENABLE Register (offset = 298h) [reset = 0h]
DDRPLL_TENABLE is shown in Figure 2-155 and described in Table 2-171.
Load the M, N, SD and SELFREQDCO dividers of the particular ADPLLLJ.
Figure 2-155. DDRPLL_TENABLE Register
31
30
29
28
27
26
Reserved
R-0h
23
22
21
20
19
18
Reserved
R-0h
15
14
13
12
11
10
Reserved
R-0h
7
6
5
4
3
2
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
PRCM Registers
25
24
17
16
9
8
1
0
TENABLE
R/W-0h
Bit
31-1
0
Field
Reserved
TENABLE
Table 2-171. DDRPLL_TENABLE Register Field Descriptions
Type
R
R/W
Reset
0h
0h
Description
M, N. SD and SELFREQDCO latch (active rise edge)
SPRUGZ8D – 14 November 2011 – Revised April 2013
Power, Reset, and Clock Management (PRCM) Module 655
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